Lab 4 - Sequential Code

I. Introduction

            The 4th Laboratory Design Exercise is about a program in VHDL that can generate a program Counter. Specifically, a Mod-9 counter. First of all, counters are circuits that cycle through a specified number of states.

There are two types of counters:

1. Synchronous (parallel) counter

   -Synchronous counters apply the same clock to all flip-flops.

2. Asynchronous (ripple) counter

   -Asynchronous or ripple counters allow some flip-flop outputs to be used as a source of      clock for other flip-flops. The flip-flops do not change states at exactly the same time        as they do not have a common clock pulse.

Mod-9 counter is an example of an applied Asynchronous (ripple) counter. This experiment can be made by studying the powerpoint lecture about the Mod-9 counter.

II. Objectives
           
            To be able to create a sequential logic circuit with sequential code.

III. Conceptual Framework

IV. Data and Results


library ieee;

use ieee.std_logic_1164.all;

entity fourpointone is

port(reset, clk, pause,setvalue : in BIT;

output : OUT BIT;

u : IN INTEGER RANGE 0 TO 9;

q,t : out bit_vector(3 downto 0));

end fourpointone;

architecture four of fourpointone is

BEGIN

PROCESS (clk, reset, pause)

VARIABLE temp : INTEGER RANGE 0 TO 10 := 0;
BEGIN

IF (clk'EVENT AND clk = '1') THEN 

if (pause = '1') THEN

temp := temp;

else

temp := temp + 1;

output <= '0';

end if;

IF (temp = 10) THEN

temp := 0;

output <= '1';

else

output <= '0';

END IF;

END IF;

IF (reset = '0') THEN


temp := 0;

END IF;

CASE temp IS

WHEN 0 => q <= "0000" ;

WHEN 1 => q <= "0001" ;

WHEN 2 => q <= "0010" ;

WHEN 3 => q <= "0011" ;

WHEN 4 => q <= "0100" ;

WHEN 5 => q <= "0101" ;

WHEN 6 => q <= "0110" ;

WHEN 7 => q <= "0111" ;

WHEN 8 => q <= "1000" ;

WHEN 9 => q <= "1001" ;

WHEN OTHERS => null;

END CASE;

CASE u IS

WHEN 0 => t <= "0000" ;

WHEN 1 => t <= "0001" ;

WHEN 2 => t <= "0010" ;

WHEN 3 => t <= "0011" ; 

WHEN 4 => t <= "0100" ;

WHEN 5 => t <= "0101" ;

WHEN 6 => t <= "0110" ;

WHEN 7 => t <= "0111" ;

WHEN 8 => t <= "1000" ;

WHEN 9 => t <= "1001" ;

WHEN OTHERS => null;

END CASE;

IF (setvalue = '0') THEN

temp := u;

END IF;

END PROCESS ;

END four;

Block Diagram



V.Analysis

             In this experiment, a mod-9 counter was presented having the functions count, set, reset and pause. We have errors in assigning the pins because this is the first time we use the buttons for setting an input. We also committed errors in the functioning of the pause button. It is an important function because it is a combinational function with the set and reset and clk buttons.

VI. Conclusion

            In this experiment, the group was able to create a sequential logic circuit having a sequential code. Also the members of the group were able to improve some skills in debugging and programming the code particularly in the conditional and case statements of the program. And just like the previous lab experiments, analyzing the data flow of the program is very significant for the experiment to be a success.