Lab 2 - VHDL Familiarization

I. Introduction

       
           VHDL is a Hardware Description Language specially introduced for Digital Circuit Design and used by Electronics, Electrical & Computer Engineers. At the present time all the devices have a Digital part or going to be digitalized; hence there is a great demand of VHDL in the market. It is very easy to design complex digital circuits like Microprocessors, DSP chips, Telecom IC’s, etc. through VHDL. 

II. Objective

            To be able to implement logic circuit design in VHDL codes

III. Conceptual Framework

(Block Diagram of Decoder)

(Block Diagram of Multiplexer)

IV. Data & Results

DECODER

library IEEE;

use IEEE.std_logic_1164.all;

entity DEC is

port( A, B, C, D : in bit;

        E, F, G, H, I, J, K : out bit );

end DEC;

architecture DEC1 of DEC is

begin

E <= NOT((NOT A AND B AND D) OR

(A AND NOT B AND NOT C) OR

(NOT B AND NOT D) OR

(NOT A AND C) OR

(B AND C));

F <= NOT((NOT A AND NOT C AND NOT D) OR

(NOT A AND C AND D) OR

(A AND NOT C AND D) OR

(NOT B AND NOT C) OR

(NOT B AND NOT D));

G <= NOT((NOT B AND NOT C) OR

(NOT B AND D) OR

(NOT C AND D) OR

(NOT A AND B) OR

(A AND NOT B));

H <= NOT((NOT B AND NOT C AND NOT D) OR

(NOT B AND C AND D) OR

(NOT A AND C AND NOT D) OR

(B AND NOT C AND D) OR

(A AND B AND NOT D) OR

(A AND NOT C));

I <= NOT((NOT B AND NOT D) OR

(C AND NOT D) OR

(A AND B) OR

(A AND C));

J <= NOT((NOT B AND NOT C AND NOT D) OR

(NOT A AND B AND NOT C) OR

(B AND C AND NOT D) OR

(A AND C) OR

(A AND NOT B));

K <= NOT((NOT B AND C) OR

(B AND NOT C) OR

(B AND NOT D) OR A); 

end DEC1;

MULTIPLEXER

library IEEE;

use IEEE.std_logic_1164.all;

entity MUX is

port( s0, s1, s2, a, b, c, d, e, f, g, h : in bit;

y : out bit );

end MUX;

architecture MUX1 of MUX is

begin

y <= (a AND NOT s0 AND NOT s1 AND NOT s2) OR

(b AND NOT s0 AND NOT s1 AND s2) OR

(c AND NOT s0 AND s1 AND NOT s2) OR

(d AND NOT s0 AND s1 AND s2) OR

(e AND s0 AND NOT s1 AND NOT s2) OR

(f AND s0 AND NOT s1 AND s2) OR

(g AND s0 AND s1 AND NOT s2) OR

(h AND s0 AND s1 AND s2);

end MUX1;

V. Analysis

            In this experiment, programming defines the whole circuit design. We have made some errors in the program because we are not too familiar with the other functions of Quartus II. But the good thing is we have the notes in the powerpoint and we use the functions that is specified in the lecture. So this experiment was easy because of the you only need to know the functions in the software and you have to analyze the problem. 

VI. Conclusion

            In this experiment, our group were able to implement logic circuit design using VHDL codes. In our case, we use the software "Quartus II" tool to create the VHDL code. The whole experiment focused in programming. Having a little background in programming in our other previous subjects, it made easy for us to do the programming. Although some errors occur, you cannot avoid these errors but the good thing is the program directs us to the error of the program. And that made our program become a success.