Lab 5 - 99 Counter

I. Introduction

            Laboratory Design Exercise 5 is just like the Lab 4 which uses a Mod-9 counter. But in this exercise we need to use a block diagram of the Lab 4 and manipulate it to have an output of 0-99 counter.

II. Objectives

            To be able to create a 99 counter with previous code.


III. Conceptional Framework

IV. Data and Result


library ieee;
use ieee.std_logic_1164.all;

entity fivepointone is

port(a, a3, e, s : in  BIT;
output2 : OUT BIT;
k  : IN INTEGER RANGE 0 TO 9;
y,h : out bit_vector(3 downto 0));

end fivepointone;

architecture five of fivepointone is

BEGIN

PROCESS (a3, a, e)

VARIABLE temp : INTEGER RANGE 0 TO 10 := 0;

BEGIN
IF (a3'EVENT AND a3 = '1') THEN
if (e = '1') THEN
temp := temp;
else
temp := temp + 1;

output2 <= '0';
end if;
IF (temp = 10) THEN
temp := 0;

  output2 <= '1';
else
output2 <= '0';
END IF;
END IF;
IF (a = '0') THEN
temp := 0;
END IF;

CASE temp IS

WHEN 0 => y <= "0000" ;
WHEN 1 => y <= "0001" ;
WHEN 2 => y <= "0010" ;
WHEN 3 => y <= "0011" ;
WHEN 4 => y <= "0100" ;
WHEN 5 => y <= "0101" ;
WHEN 6 => y <= "0110" ;
WHEN 7 => y <= "0111" ;
WHEN 8 => y <= "1000" ;
WHEN 9 => y <= "1001" ;
WHEN OTHERS => null;
END CASE;

CASE k IS

WHEN 0 => h <= "0000" ;
WHEN 1 => h <= "0001" ;
WHEN 2 => h <= "0010" ;
WHEN 3 => h <= "0011" ;
WHEN 4 => h <= "0100" ;
WHEN 5 => h <= "0101" ;
WHEN 6 => h <= "0110" ;
WHEN 7 => h <= "0111" ;
WHEN 8 => h <= "1000" ;
WHEN 9 => h <= "1001" ;
WHEN OTHERS => null;

END CASE;
IF (s = '0') THEN
temp := k;

END IF;

END PROCESS ;

END five;


Block Diagram

V. Analysis

            In this experiment, the 99counter is only similar to the previous experiment. The only difference is that it must produce two digit displays in the seven segment display. We have some troubles in the display of two digits. The ones digit is in the left side and the tens digit is in the right side. But the whole functions are working. We find it difficult to assign the pins for the seven segment display.

VI. Conclusion

           In this experiment, the group was able to create a 99 counter with sequential code having 2 seven segment display. This was made easy by the group because it was just the same with the previous experiment. The only difference is the number of output display that would count for 99 digits. And still the group members have practiced their skills in programming and debugging the code for errors. Lastly, the data flow must still be analyze every time for the group to perform the experiment well.

Lab 4 - Sequential Code

I. Introduction

            The 4th Laboratory Design Exercise is about a program in VHDL that can generate a program Counter. Specifically, a Mod-9 counter. First of all, counters are circuits that cycle through a specified number of states.

There are two types of counters:

1. Synchronous (parallel) counter

   -Synchronous counters apply the same clock to all flip-flops.

2. Asynchronous (ripple) counter

   -Asynchronous or ripple counters allow some flip-flop outputs to be used as a source of      clock for other flip-flops. The flip-flops do not change states at exactly the same time        as they do not have a common clock pulse.

Mod-9 counter is an example of an applied Asynchronous (ripple) counter. This experiment can be made by studying the powerpoint lecture about the Mod-9 counter.

II. Objectives
           
            To be able to create a sequential logic circuit with sequential code.

III. Conceptual Framework

IV. Data and Results


library ieee;

use ieee.std_logic_1164.all;

entity fourpointone is

port(reset, clk, pause,setvalue : in BIT;

output : OUT BIT;

u : IN INTEGER RANGE 0 TO 9;

q,t : out bit_vector(3 downto 0));

end fourpointone;

architecture four of fourpointone is

BEGIN

PROCESS (clk, reset, pause)

VARIABLE temp : INTEGER RANGE 0 TO 10 := 0;
BEGIN

IF (clk'EVENT AND clk = '1') THEN 

if (pause = '1') THEN

temp := temp;

else

temp := temp + 1;

output <= '0';

end if;

IF (temp = 10) THEN

temp := 0;

output <= '1';

else

output <= '0';

END IF;

END IF;

IF (reset = '0') THEN


temp := 0;

END IF;

CASE temp IS

WHEN 0 => q <= "0000" ;

WHEN 1 => q <= "0001" ;

WHEN 2 => q <= "0010" ;

WHEN 3 => q <= "0011" ;

WHEN 4 => q <= "0100" ;

WHEN 5 => q <= "0101" ;

WHEN 6 => q <= "0110" ;

WHEN 7 => q <= "0111" ;

WHEN 8 => q <= "1000" ;

WHEN 9 => q <= "1001" ;

WHEN OTHERS => null;

END CASE;

CASE u IS

WHEN 0 => t <= "0000" ;

WHEN 1 => t <= "0001" ;

WHEN 2 => t <= "0010" ;

WHEN 3 => t <= "0011" ; 

WHEN 4 => t <= "0100" ;

WHEN 5 => t <= "0101" ;

WHEN 6 => t <= "0110" ;

WHEN 7 => t <= "0111" ;

WHEN 8 => t <= "1000" ;

WHEN 9 => t <= "1001" ;

WHEN OTHERS => null;

END CASE;

IF (setvalue = '0') THEN

temp := u;

END IF;

END PROCESS ;

END four;

Block Diagram



V.Analysis

             In this experiment, a mod-9 counter was presented having the functions count, set, reset and pause. We have errors in assigning the pins because this is the first time we use the buttons for setting an input. We also committed errors in the functioning of the pause button. It is an important function because it is a combinational function with the set and reset and clk buttons.

VI. Conclusion

            In this experiment, the group was able to create a sequential logic circuit having a sequential code. Also the members of the group were able to improve some skills in debugging and programming the code particularly in the conditional and case statements of the program. And just like the previous lab experiments, analyzing the data flow of the program is very significant for the experiment to be a success.

Lab 3 - Concurrent Code and Symbol Interfacing

I. Introduction


           Unlike Sequential Logic Circuits whose outputs are dependant on both their present inputs and their previous output state giving them some form of Memory, the outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic "0" or logic "1", at any given instant in time as they have no feedback, and any changes to the signals being applied to their inputs will immediately have an effect at the output. In other words, in a Combinational Logic Circuit, the output is dependant at all times on the combination of its inputs and if one of its inputs condition changes state so does the output as combinational circuits have "no memory", "timing" or "feedback loops".

II. Objective
           To be able to implement combinational logic circuits with concurrent code and interface their symbols with each other


III. Conceptual Framework





IV. Data & Results

3.1 Create a multiplexer for two 4 bits numbers
library IEEE;

use IEEE.std_logic_1164.all;


entity twone is

port (A, B : IN STD_LOGIC_VECTOR(3 downto 0);

S : IN BIT;

X : OUT STD_LOGIC_VECTOR(3 downto 0));

end twone;

architecture fourbit of twone is

begin

process (S)

begin

if (S = '0') then

X<=A;

else

X<=B;

end if;

end process;

end fourbit;


3.2 Design a Comparator for two 4 bits numbers using VHDL. If A>B, the output is 1.
LIBRARY ieee;

USE ieee.std_logic_1164.all;


entity twofour is

port (x, y : IN BIT_VECTOR (3 downto 0);

z : OUT BIT);

end twofour;


architecture behavior of twofour is

begin

z<= '1' when (x>y) else '0';

end behavior;

3.3 Design comparator for two 4 bits numbers in 7-segment. The 7-segment will display the greater number







V. Analysis


           In this experiment, the modules of the comparator and multiplexer has to be implemented as a single working circuit wherein combinational logic circuit would be implemented with concurrent codes and their symbol would interfere with each other. Concurrent codes are a form of superimposed codes that can be decoded efficiently and so we observed on how the circuit will respond given with two different inputs.


VI. Conclusion


           In this experiment, our group was able to implement combinational logic circuit with concurrent codes. At first, we have some difficulties in understanding the flow of the whole circuit. But then, we took the solution of understanding the flow of the inputs and outputs in the comparator. And with the resultant output of the comparator, we took it as an input for the multiplexer circuit design.

Lab 2 - VHDL Familiarization

I. Introduction

       
           VHDL is a Hardware Description Language specially introduced for Digital Circuit Design and used by Electronics, Electrical & Computer Engineers. At the present time all the devices have a Digital part or going to be digitalized; hence there is a great demand of VHDL in the market. It is very easy to design complex digital circuits like Microprocessors, DSP chips, Telecom IC’s, etc. through VHDL. 

II. Objective

            To be able to implement logic circuit design in VHDL codes

III. Conceptual Framework

(Block Diagram of Decoder)

(Block Diagram of Multiplexer)

IV. Data & Results

DECODER

library IEEE;

use IEEE.std_logic_1164.all;

entity DEC is

port( A, B, C, D : in bit;

        E, F, G, H, I, J, K : out bit );

end DEC;

architecture DEC1 of DEC is

begin

E <= NOT((NOT A AND B AND D) OR

(A AND NOT B AND NOT C) OR

(NOT B AND NOT D) OR

(NOT A AND C) OR

(B AND C));

F <= NOT((NOT A AND NOT C AND NOT D) OR

(NOT A AND C AND D) OR

(A AND NOT C AND D) OR

(NOT B AND NOT C) OR

(NOT B AND NOT D));

G <= NOT((NOT B AND NOT C) OR

(NOT B AND D) OR

(NOT C AND D) OR

(NOT A AND B) OR

(A AND NOT B));

H <= NOT((NOT B AND NOT C AND NOT D) OR

(NOT B AND C AND D) OR

(NOT A AND C AND NOT D) OR

(B AND NOT C AND D) OR

(A AND B AND NOT D) OR

(A AND NOT C));

I <= NOT((NOT B AND NOT D) OR

(C AND NOT D) OR

(A AND B) OR

(A AND C));

J <= NOT((NOT B AND NOT C AND NOT D) OR

(NOT A AND B AND NOT C) OR

(B AND C AND NOT D) OR

(A AND C) OR

(A AND NOT B));

K <= NOT((NOT B AND C) OR

(B AND NOT C) OR

(B AND NOT D) OR A); 

end DEC1;

MULTIPLEXER

library IEEE;

use IEEE.std_logic_1164.all;

entity MUX is

port( s0, s1, s2, a, b, c, d, e, f, g, h : in bit;

y : out bit );

end MUX;

architecture MUX1 of MUX is

begin

y <= (a AND NOT s0 AND NOT s1 AND NOT s2) OR

(b AND NOT s0 AND NOT s1 AND s2) OR

(c AND NOT s0 AND s1 AND NOT s2) OR

(d AND NOT s0 AND s1 AND s2) OR

(e AND s0 AND NOT s1 AND NOT s2) OR

(f AND s0 AND NOT s1 AND s2) OR

(g AND s0 AND s1 AND NOT s2) OR

(h AND s0 AND s1 AND s2);

end MUX1;

V. Analysis

            In this experiment, programming defines the whole circuit design. We have made some errors in the program because we are not too familiar with the other functions of Quartus II. But the good thing is we have the notes in the powerpoint and we use the functions that is specified in the lecture. So this experiment was easy because of the you only need to know the functions in the software and you have to analyze the problem. 

VI. Conclusion

            In this experiment, our group were able to implement logic circuit design using VHDL codes. In our case, we use the software "Quartus II" tool to create the VHDL code. The whole experiment focused in programming. Having a little background in programming in our other previous subjects, it made easy for us to do the programming. Although some errors occur, you cannot avoid these errors but the good thing is the program directs us to the error of the program. And that made our program become a success. 

Lab 1 - Quartus II Familiarization

I. Introduction

           Altera Qurtus is a design software from Altera that involves the implementation ofVHDL and Verilog for hardware description, Visual edition of logic circuits, and Vector waveform simulation.

           Quartus II is a software tool produced by Altera for analysis and synthesis of VHDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.


II. Objective
To be able to create Logic circuit design in Quartus II

III. Conceptual Framework



(Flowchart of Decoder)



(Flowchart of Multiplexer)

IV. Data & Results

Decoder














Multiplexer





















V. Analysis

           In this experiment, we have observed that this program is very useful in Software design because Altera includes advanced integrated synthesis that fully supports VHDL and provides options to control the synthesis process. With this synthesis support, the Quartus II software provides a complete, easy-to-use solution.



VI. Conclusion

           In this experiment, our group were able to create a Logic circuit design using Altera Quartus II. This experiment focuses on block diagrams of a Logic circuit design, so it became easy for us because we already have a background on creating a Logic circuit design during our laboratory in Logic Circuits. And we are already familiar with the different Logic gates and how to input output in a Logic circuit design.